Integrated circuits (ICs) are commonly made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or FET features are shrunk to shrink corresponding device minimum dimensions including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions, e.g., channel layer depth, gate dielectric thickness, junction depths and etc. Shrinking device size increases device density and device performance, as well as reduces device-operating conditions, i.e., chip and correspondingly, device supply voltages and voltage swings. Consequently, as a result of scaling, otherwise seemingly neglectable device-to-device variations (e.g., length, width, threshold and etc.) have caused serious design problems, especially in signal critical circuits such as memory sense amplifiers.
A typical CMOS circuit includes paired complementary devices, i.e., an N-type FET (NFET) paired with a corresponding P-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. So, for example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND).
An ideal static random access memory (SRAM) cell includes a balanced pair of cross-coupled inverters storing a single data bit with a high at the output of one inverter and a low at the output of the other. A pair of pass gates (also ideally, a balanced pair of FETs) selectively connects the complementary outputs of the cross-coupled inverter to a corresponding complementary pair of bit lines. A word line connected to the gates of the pass gate FETs selects the cell, connecting the cell contents to the corresponding complementary pair of bit lines. An N by M SRAM array is organized as N rows of word lines by M columns of line pairs. Accessing a K bit single word (for a read or a write) from the array entails driving one of the N word lines. During a read, each cell on the selected word line couples its contents to its corresponding bit line pair through NFET pass gates. Each cell on a selected column line may be coupled to a simple sense amplifier (sense amp); ideally, a matched pair of cross-coupled common-source devices connected between a bit line pair and an enable source line. Since the bit line pair is typically pre-charged to some common voltage, initially, the internal (to the cell) low voltage rises until one of the bit line pairs droops sufficiently to develop a small difference signal (e.g., 30 mV) on the bit line pair.
Since a design shape printed and formed at different locations always has some variation, albeit minor variation, in the way it prints, imbalances in a matched cell device pair or a matched sense amp pair is inevitable. These imbalances unbalance the pair and may seriously erode the sense signal margin and even cause data sense errors. This erosion may be worse still in a partially depleted (PD) silicon on insulator (SOI) CMOS SRAM cells and circuits, because PD SOI devices are subject to what is known as floating body effects. Floating body effects, also known simply as body effects or as history effects, occur in completely or partially isolated (e.g., where body resistance may have rendered body contacts ineffective) devices, where the device substrate or body is floating or essentially floating. As a floating body device switches off, charge (i.e., from majority carriers) remains in the device body beneath the channel. Device leakage and parasitic bipolar effects may add to the charge. Charge builds at isolated devices as the chip operates because the charge from fast switching devices is injected into locally isolated body pockets faster than it dissipates. Eventually, the injected charge reaches some steady state value that acts as a substrate bias, e.g., shifting the threshold voltage (VT) for the device. This steady state change depends upon each particular device's switching history and so is also known as the history effects for the particular device. The result of the body effects may be that two identical-by-design adjacent devices exhibit some difference that may be time varying, e.g., from changing circuit conditions during read and write operations. Consequently, the initial states of cell transistors (cell history) as well as gate-to-body tunneling current (that may further imbalance cell symmetry) can be critical to cell stability. Thus, body effects can unbalance a matched pair of devices in a sense amp, for example. The inadequately balanced sense amplifier may read a signal that is not there or self-trigger, sensing before the signal has developed, e.g., to read a residual signal from a partial prior restore.
Thus, there is a need for improved SRAM data sense reliability, and especially for an improved SRAM data sense circuit for PD SOI CMOS SRAMs with reduced sensitivity to body effects, local device variations, mismatches in matched device pairs and increases in device body resistance.